This invention relates to protecting integrated circuits from damage from electrostatic discharge. In this invention the protection is accomplished without the use of a series resistor in the signal path, which makes this invention particularly suitable for high speed circuitry.
Electrostatic discharge (ESD) occurs when large voltage pulses due to static electricity occur at the leads of an integrated circuit (IC). These large voltage pulses can cause the breakdown of insulating layers, short circuiting between conducting paths, or overheating or evaporation of metal or silicon pathways within the IC, leading to failure of the IC. With increased density ICs, the reduction in the width of lines and insulating spaces within the ICs has made them more susceptible to damage from ESD. Emphasis on increased reliability has required the addition of ESD protection circuitry to the input and output pins of ICs. FIG. 1 shows one form of ESD protection circuit known in the art. An input pin 10 is connected through a series resistor 12 of value R to an internal signal line 14. The internal signal line 14 connects to the protected circuit of the IC. A first diode 16 has its anode connected to the internal signal line 14, and its cathode connected to a supply line to the positive supply voltage V.sub.DD, typically +5 volts. A second diode 18 has its cathode connected to the internal signal line 14, and its anode connected to a ground line to the ground or supply reference point V.sub.SS. An input voltage V.sub.IN on input pin 10 will travel through series resistor 12 to the internal signal line 14 and to the protected circuit of the IC.
The series resistor 12 serves three purposes. It limits the amount of current that can be drawn, protecting the diodes from excessive current. It also delays the rise of sharp voltage pulses by introducting R-C type delay on the signal line. The series resistor also acts as part of a voltage divider to reduce the voltage appearing on the internal signal line 14.
FIG. 2 shows the input current IIN vs. input voltage V.sub.IN characteristics of the protection circuit of FIG. 1. In the normal operating region 20, no diode conduction occurs and input signals are passed from input pin 10 through the series resistor 12 to the internal signal line 14 to the protected circuit. In the over voltage region 22, when the input voltage V.sub.IN is above the positive supply voltage V.sub.DD by more than one diode voltage drop V.sub.be, diode 16 will be forward biased and conduct, drawing input current I.sub.IN limited by the value R of the series resistor 12. In the negative voltage region 24, when the input voltage V.sub.IN is below, or negative with respect to, the ground or supply reference point V.sub.SS by more than one diode voltage drop V.sub.be, diode 18 will be forward biased and conduct, drawing input current I.sub.IN limited by the value R of the series resistor 12. In this manner excessive positive or negative input voltages are dissipated by input current I.sub.IN to the positive supply voltage V.sub.DD or ground V.sub.SS. For a typical positive supply voltage V.sub.DD of 5.0 volts and a diode voltage drop V.sub.be of 0.6 volts, conduction will begin in the over voltage region 22 at V.sub.DD +V.sub.be or 5.0+0.6=5.6 volts. Conduction will begin in the negative voltage region 24 at -V.sub.b3 or -0.6 volts.
Tolerance to ESD is typically measured by charging a 100 picofarad capacitor to a high voltage and then connecting the capacitor through a 1.5 K ohm resistor to the various pins of the IC. The protection circuit of FIG. 1 is adequate for ESD voltages up to 800 volts positive or negative. However, protection up to 2000 volts and above is desired, and the protection circuit of FIG. 1 has several disadvantages.
First, the use of a series resistor 12 in the signal path reduces the maximum rate of signal change possible for signals on the signal path from the input pin 10 to the protected circuit, due to R-C type delays as the series resistor 12 interacts with the input capacitance of the protected circuit and the stray capacitance of the IC packaging and silicon die. A protection circuit without the use of a series resistor is desired to allow protection of high speed circuits.
Second, the series resistor 12 limits the amount of input current I.sub.IN that can be drawn to dissipate very large input voltages. A protection circuit without a series resistor would draw a larger input current and provide greater dissipation of very large input voltages.
Third, current through the ESD protection diodes 16 and 18 begins at input voltage levels just one diode voltage drop V.sub.be above the positive supply voltage V.sub.DD, at about 5.6 volts, whereas protection is not required until the input voltage approaches the breakdown voltage BV of the protected circuit, typically 20-30 volts for MOS circuitry or 30-50 volts for bipolar circuitry. Input current I.sub.IN in the interim voltage range of 5.6 to 20 volts is wasteful and creates undesirable heat buildup. A protection circuit without input current until approaching the level of the breakdown voltage is desired to reduce power dissipation and reduce heat buildup.
Finally, where the diodes are fabricated into the same silicon substrate as other circuitry, they must be spaced away from the other circuitry or be surrounded by guard bands to prevent minority carriers injected into the substrate by the diodes from affecting the operation of the other circuitry. A protection circuit that can be fabricated in a smaller area without affecting other circuitry is desired.